慶應義塾大学山中研究室は、情報通信研究機構(NICT)、KDDI研究所と共同し、LANの標準規格イーサネットである拠点間を結ぶ、イーサネットの仮想専用線を自動で相互接続する技術を開発し、科学新聞(1月9日)、日本情報産業新聞(1月12日)、日刊工業新聞(1月13日)に掲載されました。
今回の実験では、通信事業者間の光ネットワークで回線を自動設定するプロトコル「GMPLS RSVP-TE」（generalized multi-protocol label switching resource reservation protocol traffic engineering extension）によるイーサネットVLAN自動設定技術を用いた相互接続実験に成功しました。

M1の岡崎君が、電子情報通信学会フォトニックネットワーク研究会
から、表彰されました。

【PN研究賞】
種村拓夫・武田浩司・中野義昭（東大）
「フェーズアレイ型1×N半導体光スイッチの試作と理論検討」 (PN2007-65)

【PN若手研究賞】
高木衛（東大）
「共有波長資源配分比率可変型400Gb/sハイブリッド光交換ノードの実証実験」
(PN2008-40)
後藤洋臣（阪大）
「波形整形を用いた入力信号歪みの導入による全光強度イコライザの
補償範囲拡大の範囲」(PN2007-85)
岡崎裕介（慶大）
「広域分散コンピューティングを用いた遅延を考慮したスケールフリーディスプレイ構築法」
(PN2008-28)

M1の岡崎君，高君が，11月に韓国で行われた国際会議IEEE international student paper contest 2008で発表しました．
岡崎くんはBronze prizeを獲得しました．
発表者，タイトルは以下のとおりです

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タイトル: “Delay-Aware Scale-Free Display System under ubiquitous Grid　Networking (uGrid) Environment”

著者: Yusuke Okazaki, Yuki Susa, Ryota Usui, Yutaka Arakawa, Satoru Okamoto, Naoaki Yamanaka

要旨: New scalable display system in a ubiquitous Grid networking (uGrid) called scale-free display system is proposed. Tiled display system which can visualize large high-resolution　images has been becoming famous. However, the more display size grow large, the more hard to establish the system. Also,a study of widely distributed computing or uGrid has been　growing. In this paper, we propose scale-free display system under distributed computing network and optical broad band network. In proposed system, computing resources are widely distributed in the network, so distances from each computing resource to the tiled display are different. Thus, to synchronize all frames of image, computing resources which have almost same delay to the tiled display have to be selected in case that the system starts. For this reason, we consider the method to select the computing resources. Also we examine the characteristic of delay in power-law network under the assumption that the proposed system will be applied to power-law network.

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タイトル: “Traffic Engineering based on Experimentation in On-chip Virtual Network on Dynamically Reconfigurable Processor”

著者: Shan Gao, Taku Kihara, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka, Kosuke Shiba

要旨: In recent years, traffic engineering has widely researched to guarantee QoS. It is important that not only link cost, but also several metrics should be considered in next generation traffic engineering. A high-speed traffic engineering method is required, because the complexity increases when more than one metric is considered. In this paper, different from conventional mathematical approach, we describe an experimental traffic engineering method using on-chip virtual network implemented on reconfigurable processor. Links and nodes in virtual network are constructed by several PEs (processor elements) in DAPDNA-2. We obtain the realistic traffic fluctuation through the behavior of packets that is in the on-chip virtual network. In this paper, as first trial to achieve our goal, we implemented virtual network construction method and confirmed basic path calculation algorithm on the constructed virtual network.