Mr. Ishikawa, who has graduated from our laboratory, received the Best Paper Award for his paper about Parallel reconfigurable processor at APCC 2008.

The title and abstract of his paper are as follows.

Title: “Fast Replica Allocation Method by Parallel Calculation on DAPDNA-2”
Authors: Hiroyuki Ishikawa, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka, and Kosuke Shiba
Abstract: This paper proposes a fast calculation method of the replica placement problem, which is implemented on reconfigurable processor DAPDNA-2 of IPFlex Inc. Our proposed method divides the combination optimally and performs pipeline operation. Beeler’s algorithm can calculate all combinations in ascending order but it has data dependence. It’s difficult to calculate any pattern because each data increases irregularly. In order to solve this problem, we propose the new algorithm that generates any order pattern. In addition, the optimal number of partitions depends on the number of combinations and calculation clocks of Beeler’s algorithm. In order to solve this problem, we think about the optimal division number in theory. While the time complexity of conventional method is proportional to the number of combinations, that of proposed method is proportional to the square root of the number of combinations. Experimental results show that the proposed algorithm reduces the execution time by 40 times compared to Intel Pentium 4 (2.8GHz).