Mr. Ishii and Dr. Okamoto’s paper co-worked with Dr. Imajuku of NTT communications etc. was published in the IEEE Communications Magazine.

Magazine: IEEE Communications Magazine, Vol.47, No.2, pp.168-175, February 2009.

Title: Multi-Area MPLS/GMPLS Interoperability Trial Over ROADM/OXC Network

Authors: Wataru Imajuku, Eiji Oki (NTT Laboratories), Rajiv Papneja (Isocore), Shinichiro Morishita (TOYO Corporation), Kenichi Ogaki, Masanori Miyazawa (KDDI R&D Laboratories Inc.), Keiji Miyazaki (Fujitsu Laboratories Ltd.), Hiroaki Nakazato (Fujitsu Ltd.), Hidetsugu Sugiyama, John Allen (Juniper Networks), Shinichi Hasegawa, Nobuhiro Sakuraba (ITOCHU Techno-Solutions Corporation), Itaru Nishioka (NEC Corporation), Shoichiro Seno (Mitsubishi Electric Corporation), Yoshihiro Nakahira (Oki Electric Industry Co., Ltd.), Daisuke Ishii, Satoru Okamoto (Keio University), Tara Van Unen (Agilent Technologies, Inc.), Mark Blumhardt (Alcatel USA Inc.), Hari Rakotoranto (Cisco Systems, Inc.), Vijay Pandian (Sycamore Networks)

Abstract: This article describes the first multi-area Multi-Protocol Label Switching (MPLS) and Generalized MPLS interoperability trial over Reconfigurable Optical Add/Drop Multiplexer (ROADM) and Optical Cross-Connect (OXC) network. The interoperability trial demonstrated the routing of Label Switched Paths (LSPs) over a multi-area GMPLS controlled ROADM/OXC network and the control of Ethernet over MPLS (EoMPLS) transport service on top of the GMPLS network. The trial was conducted using various network elements provided by 14 institutions and was carried out at Tokyo and Virginia. This article introduces the motivation of the trial, technical issues related to controlling multi-area MPLS/GMPLS networks, test network topology, and experimental results. The results show that the interior gateway routing protocol based multi-area routing architecture is a promising solution for the nationwide deployment of GMPLS networks within a carrier domain. Furthermore, this article discusses the technical issues of routing constraints in ROADM/OXC networks and the limit of multi-area routing without Path Computation Element Protocol (PCEP).

Our lab succeeded in the interconnection of the path computation server that calculated the route of an optical network between a lot of careers, and the success was published in some newspapers.

Mr. Okazaki received the young researchers award from the IEICE Technical Committee on Photonic Network (PN).
Congratulations!!!!

Mr. Okazaki and Mr. Gao made presentations at the IEEE international student paper contest 2008 in November.
Mr. Okazaki won the Bronze prize．
The titles and authors are as follows.

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Title: “Delay-Aware Scale-Free Display System under ubiquitous Grid　Networking (uGrid) Environment”

Authors: Yusuke Okazaki, Yuki Susa, Ryota Usui, Yutaka Arakawa, Satoru Okamoto, Naoaki Yamanaka

Abstract: New scalable display system in a ubiquitous Grid networking (uGrid) called scale-free display system is proposed. Tiled display system which can visualize large high-resolution　images has been becoming famous. However, the more display size grow large, the more hard to establish the system. Also,a study of widely distributed computing or uGrid has been　growing. In this paper, we propose scale-free display system under distributed computing network and optical broad band network. In proposed system, computing resources are widely distributed in the network, so distances from each computing resource to the tiled display are different. Thus, to synchronize all frames of image, computing resources which have almost same delay to the tiled display have to be selected in case that the system starts. For this reason, we consider the method to select the computing resources. Also we examine the characteristic of delay in power-law network under the assumption that the proposed system will be applied to power-law network.

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Title: “Traffic Engineering based on Experimentation in On-chip Virtual Network on Dynamically Reconfigurable Processor”

Authors: Shan Gao, Taku Kihara, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka, Kosuke Shiba

Abstract: In recent years, traffic engineering has widely researched to guarantee QoS. It is important that not only link cost, but also several metrics should be considered in next generation traffic engineering. A high-speed traffic engineering method is required, because the complexity increases when more than one metric is considered. In this paper, different from conventional mathematical approach, we describe an experimental traffic engineering method using on-chip virtual network implemented on reconfigurable processor. Links and nodes in virtual network are constructed by several PEs (processor elements) in DAPDNA-2. We obtain the realistic traffic fluctuation through the behavior of packets that is in the on-chip virtual network. In this paper, as first trial to achieve our goal, we implemented virtual network construction method and confirmed basic path calculation algorithm on the constructed virtual network.

Ms. Terasawa’s paper about the fault recovery in L2 network was accepted in ICC.

Title: “Recover-Forwarding Method In Link Failure With Pre-established Recovery Table For Wide Area Ethernet”

Authors: Midori Terasawa, Masahiro Nishida, Sho Shimizu, Yutaka Arakawa, Satoru Okamoto, Naoaki Yamanaka

Abstract: This paper proposes a fast fault recovery method for the wide area Ethernet. To achieve fast recovery, a pre-established forwarding table is introduced. The pre-established table is looked up when a fault occurs, and frames are forwarded without frame loss. Ethernet lacks of fault recovery features required in Wide Area Network (WAN) since it is originated as Local Area Network (LAN) technology. Protection or restoration is a typical method for fault recovery, but a lot of frame losses are inevitable. Our proposal can decrease frame losses since frames are forwarded without waiting for path switching to be completed to use the pre-preparation table. In addition, the proposed method can be operated with the legacy forwarding method seamlessly. The simulation results show that frame loss decreases to 40 % or less with our proposed method.

The second master grader announced the master’s theses.
The speaker and the title are shown as follows.

Ryouta Usui:
A Study on Service-Parts Discovery System and Their Connection Method for Ubiquitous Grid Networking (uGrid)

Mikio Kaneko:
A Study and Implementation on the New Generation P2P Networks using GMPLS Dynamic Path Establishment

Masahiro Nishida:
Dynamic Reconfiguration of Layer-2 Switch Architecture Triggered by Path-setup

Kazuki Irie:
A Study on Contents Download Method to Reduce Server Load in CDN

Kou Kikuta:
Establishing of Domain Tag Swapped Path on Wide Area Layer-2 Network by GMPLS controlling

Taku Kihara:
Proposal and Implementation of Fast Optimal Protection Path Calculation Algorithm Suitable for Dynamically Reconfigurable Processor DAPDNA-2

KEIO TECHNOMALL was held in Tokyo International Forum on December 19, 2008.
Yamanaka laboratory exhibited two booths.

• Active Optical Access Network -ActiON-
• Next Generation Layer2 Network Technologies

100 or more participants came to the booths in Yamanaka laboratory.
A lot of positive question and answer was done in the booths and we got a lot of valuable opinions.

Keio Techno-Mall Website

Research on active optical access network was introduced as the attractive research in the press release of KEIO TECHNO-MALL 2008

Mr. Kikuta’s letter paper about Multi-Domain VLAN Path Signaling was accepted in the IEICE Trans. on Communications.

Title: “Multi-Domain VLAN Path Signaling Method having Tag Swapping Function for GMPLS controlled Wide Area Layer-2 Network”

Mr. Kikuta’s paper about establishment of VLAN tag swapped path on the wide area layer-2 network was accepted for NFOEC2009 poster.

Title: Establishment of VLAN Tag Swapped Path on GMPLS Controlling Wide Area Layer-2 Network

Author: Kou Kikuta, Masahiro Nishida, Daisuke Ishii, Satoru Okamoto, Naoaki Yamanaka

Abstract: GMPLS controlled multi-domain end-to-end layer-2 path establishment with VLAN tag swapping is demonstrated. Two kinds of signaling　mechanisms to realize tag swapping are implemented on prototype layer-2　switch systems and both mechanisms are evaluated.