M1の岡崎君，高君が，11月に韓国で行われた国際会議IEEE international student paper contest 2008で発表しました．
タイトル: “Delay-Aware Scale-Free Display System under ubiquitous Grid Networking (uGrid) Environment”
著者: Yusuke Okazaki, Yuki Susa, Ryota Usui, Yutaka Arakawa, Satoru Okamoto, Naoaki Yamanaka
要旨: New scalable display system in a ubiquitous Grid networking (uGrid) called scale-free display system is proposed. Tiled display system which can visualize large high-resolution images has been becoming famous. However, the more display size grow large, the more hard to establish the system. Also,a study of widely distributed computing or uGrid has been growing. In this paper, we propose scale-free display system under distributed computing network and optical broad band network. In proposed system, computing resources are widely distributed in the network, so distances from each computing resource to the tiled display are different. Thus, to synchronize all frames of image, computing resources which have almost same delay to the tiled display have to be selected in case that the system starts. For this reason, we consider the method to select the computing resources. Also we examine the characteristic of delay in power-law network under the assumption that the proposed system will be applied to power-law network.
タイトル: “Traffic Engineering based on Experimentation in On-chip Virtual Network on Dynamically Reconfigurable Processor”
著者: Shan Gao, Taku Kihara, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka, Kosuke Shiba
要旨: In recent years, traffic engineering has widely researched to guarantee QoS. It is important that not only link cost, but also several metrics should be considered in next generation traffic engineering. A high-speed traffic engineering method is required, because the complexity increases when more than one metric is considered. In this paper, different from conventional mathematical approach, we describe an experimental traffic engineering method using on-chip virtual network implemented on reconfigurable processor. Links and nodes in virtual network are constructed by several PEs (processor elements) in DAPDNA-2. We obtain the realistic traffic fluctuation through the behavior of packets that is in the on-chip virtual network. In this paper, as first trial to achieve our goal, we implemented virtual network construction method and confirmed basic path calculation algorithm on the constructed virtual network.