M2の高君のオンチップジオラマネットワークを利用したトラヒックエンジニアリングに関する論文が国際会議 HPSR2009に採録されました。


タイトル: “A Novel Traffic Engineering Method using On-Chip Diorama Network on Dynamically Reconfigurable Processor DAPDNA-2”

要旨: This paper proposes a novel traffic engineering method using on-chip diorama network that consists of virtual nodes and virtual links. The diorama network is implemented on reconfigurable processor DAPDNA-2. In these years, traffic engineering has widely researched to guarantee QoS (Quality of Service). The proposal is an experimental solution with the on-chip diorama network, where virtual links and virtual nodes are constructed by some PEs (processing elements). We obtain the realistic traffic fluctuation through the behavior of virtual packets exchanged on the on-chip diorama network. In this paper, as first trial to achieve our final goal, we implemented diorama network and confirmed basic path calculation, where both functions are an essential function of our algorithm. The diorama network traffic engineering can realize more sophisticated network design like adaptive traffic balancing or multi-metric design.

D1の菊田君のマルチドメイン間のVLANパスシグナリングに関するレター論文がIEICE 英文論文誌4月号に掲載されました


IEICE Transactions on Communications, Vol. E92-B, No. 4, pp. 1353-1356, April 2009.

タイトル: “Multi-Domain VLAN Path Signaling Method having Tag Swapping Function for GMPLS controlled Wide Area Layer-2 Network”

著者: Kou Kikuta, Masahiro Nishida, Daisuke Ishii, Satoru Okamoto, and Naoaki Yamanaka

要旨: A multi-domain GMPLS layer-2 switch capable network with VLAN tag swapping is demonstrated for the first time. In this demonstration, we verify three new features, establishing path with destinating VLAN IDs, swapping VLAN ID on prototype switch, and management of VLAN IDs per domain. Using those three features, carrier-class Ethernet backbone networks witch support path route designation in multi-domain network can be established.