The IEEE Student Branch Leadership Training Workshop was held on October 4.
The purpose of this workshop is to enhance student’s leadership through a debate session.
This workshop is held every year, and Keio university participated in this workshop as a host in this year.
The discussion theme of this year is “How to improve our research efficiency.”
All students discussed this theme actively.
The Keihanna Open Lab, a project general manager of which is Dr. Yamanaka, researches the elemental technology of next generation’s optical network in cooperation with a lot of Japanese career venders.
The lab succeeded in the interconnection of the path computation server that calculated the route of an optical network between a lot of careers, and the success was announced as press release.
We exhibited the demonstration of the scale free display technology in the Yagami festival on October 14.
The K2 open campus was held on October 4.
The Keio University Shin-Kawasaki town campus (K2 town campus) is held as facilities where an up-to-date industrial-government-academic joint research is borne by cooperation and cooperation with Kawasaki City in the spring of 2000, and “Square for the Shin-Kawasaki up-to-date research boundary region” is set up based on here.
K2Campas HP
Open campus has been held K2 inside the campus every year. The Yamanaka laboratory moved to the K2 campus in 2008, and was researching. We participated in open campus.
In the Yamanaka laboratory, it was entitled, “Network basic research project for the terabit age” as a research introduction, and introduced the scale free display technology and the high-speed, optical switching technology.
Mr. Ishikawa, who has graduated from our laboratory, received the Best Paper Award for his paper about Parallel reconfigurable processor at APCC 2008.
The title and abstract of his paper are as follows.
Title: “Fast Replica Allocation Method by Parallel Calculation on DAPDNA-2”
Authors: Hiroyuki Ishikawa, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka, and Kosuke Shiba
Abstract: This paper proposes a fast calculation method of the replica placement problem, which is implemented on reconfigurable processor DAPDNA-2 of IPFlex Inc. Our proposed method divides the combination optimally and performs pipeline operation. Beeler’s algorithm can calculate all combinations in ascending order but it has data dependence. It’s difficult to calculate any pattern because each data increases irregularly. In order to solve this problem, we propose the new algorithm that generates any order pattern. In addition, the optimal number of partitions depends on the number of combinations and calculation clocks of Beeler’s algorithm. In order to solve this problem, we think about the optimal division number in theory. While the time complexity of conventional method is proportional to the number of combinations, that of proposed method is proportional to the square root of the number of combinations. Experimental results show that the proposed algorithm reduces the execution time by 40 times compared to Intel Pentium 4 (2.8GHz).